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ltc2925 1 2925fc typical application features applications description multiple power supply tracking controller with power good timeout n v core and v i/o supply tracking n microprocessor, dsp and fpga supplies n servers n communication systems l , lt, ltc and ltm are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. n flexible power supply tracking up and down n power supply sequencing n supply stability is not affected n controls three supplies without series fets n controls an optional fourth supply with a series fet n electronic circuit breaker n remote sense switch compensates for voltage drop across a series fet n supply shutdown outputs n fault output n adjustable power good timeout n available in narrow 24-lead ssop and tiny 24-lead qfn packages the ltc ? 2925 provides a simple solution to power supply tracking and sequencing requirements. by selecting a few resistors, the supplies can be con? gured to ramp-up and ramp-down together or with voltage offsets, time delays or different ramp rates. the ltc2925 controls the outputs of three independent supplies without inserting any pass element losses. for systems that require a fourth supply, or when a supply does not allow direct access to its feedback resistors, one supply can be controlled with a series fet. when the fet is used, an internal remote sense switch compensates for the voltage drop across the fet and current sense resistor, and an electronic circuit breaker provides protection from short-circuit conditions. the ltc2925 also includes a power good timeout feature that turns off the supplies if an external supply monitor fails to indicate that the supplies have entered regulation within an adjustable timeout period. 0.015 si4412ady 0.1f 0.1f 0.82f 10k v cc sensep sensen 3.3v v in 3.3v 138k 3.3v v in 1.65k 88.7k 41.2k 2.5v slave2 master 88.7k 41.2k 86.6k 100k 13k 100k rampbuf track1 track2 track3 fb2 gate ltc2925 pgtmr 0.082f sdtmr 0.47f sctmr gnd 2925 ta01 ramp 100k 1.5v slave3 86.6k dc/dc in fb = 0.8v out dc/dc in fb = 0.8v run/ss run/ss out fb3 sd3 sd2 3.3v pgi 35.7k 10 1.8v slave1 16.5k supply monitor dc/dc in fb = 1.235v run/ss out fb1 sd1 fault on 10k v in status remote rst 1v/div 3.3v 2.5v 1.8v 1.5v 10ms/div 2925 ta02a 1v/div 3.3v 2.5v 1.8v 1.5v 10ms/div 2925 ta02b
ltc2925 2 2925fc absolute maximum ratings (notes 1, 2) 1 2 3 4 5 6 7 8 9 10 11 12 top view gn package 24-lead plastic ssop 24 23 22 21 20 19 18 17 16 15 14 13 v cc sensep sensen on sdtmr sd1 sd2 sd3 rampbuf gnd fb3 track3 sctmr pgtmr pgi status fault gate ramp remote fb1 track1 track2 fb2 t jmax = 125c, = ( s 4mm) plastic qfn exposed pad (pin 25) internally connected to gnd (pcb connection optional) 10 11 12 6 5 4 3 2 1 13 14 15 16 17 18 25 on sdtmr sd1 sd2 sd3 rampbuf sensen sensep v cc sctmr pgtmr pgi gnd fb3 track3 fb2 track2 track1 status fault gate ramp remote fb1 t jmax = 125c, = ( ) ( ) ( ) ( ) ( ) + + + + ( ) ( )
ltc2925 3 2925fc electrical characteristics the l denotes the speci? cations which apply over the full operating temperature range, otherwise speci? cations are at t a = 25c. v cc = 5v unless otherwise noted. symbol parameter conditions min typ max units v cc input supply range l 2.9 5.5 v i cc input supply current i fbx = 0, i trackx = 0, i rampbuf = 0 l 1.5 3 ma i fbx = C1ma, i trackx = C1ma, i rampbuf = C3ma l 10.5 15 ma v cc(uvl) input supply undervoltage lockout v cc rising l 2.3 2.5 2.7 v v cc(uvl, hyst) input supply undervoltage lockout hysteresis 25 mv v gate external n-channel gate drive (v gate C v cc )i gate = C1a l 5 5.5 6 v i gate gate pin current gate on, v gate = 0v, no faults l C7 C10 C13 a gate off, v gate = 5v, no faults l 71013 a gate off, v gate = 5v, short-circuit or power good timeout l 52050 ma v on(th) on pin threshold voltage v on rising l 1.214 1.232 1.250 v v on(hyst) on pin hysteresis l 30 75 150 mv v on(fc) on pin fault clear threshold voltage l 0.3 0.4 0.5 v i on(in) on pin input current v on = 1.2v, v cc = 5.5v l 0 100 na v rs-sense(th) sense resistor overcurrent voltage threshold (v sensep C v sensen ) 1v < v sensep < v cc 0v < v sensep < 1v l l 40 30 50 50 60 70 mv mv i sensen sensen pin input current 0v < v sensen < v cc l C1510 a i sensep sensep pin input current 0v < v sensep < v cc l C1510 a v os ramp buffer offset (v rampbuf C v ramp )v rampbuf = v cc /2, i rampbuf = 0a l C30 0 30 mv v fault (ol) fault output low voltage i fault = 3ma l 0.2 0.4 v v sdx (ol) sdx output low voltage i sdx = 1ma, v cc = 2.3 l 0.2 0.4 v v status(ol) status output low voltage i status = 3ma l 0.2 0.4 v i ramp ramp pin input current 0v < ramp < v cc , v cc = 5.5v l 01 a v rampbuf(ol) rampbuf low voltage i rampbuf = 3ma l 90 150 mv v rampbuf(oh) rampbuf high voltage (v cc C v rampbuf )i rampbuf = C3ma l 100 200 mv i error(%) i fbx to i trackx current mismatch i error(%) = (i fbx C i trackx )/i trackx i trackx = C10a i trackx = C1ma l l 0 0 5 5 % % v trackx track pin voltage i trackx = C10a i trackx = C1ma l l 0.78 0.78 0.8 0.8 0.82 0.82 v v i fb(leak) i fb leakage current v fb = 1.5v, v cc = 5.5v l 10 na v fb(clamp) v fb clamp voltage 1a < i fb < 1ma l 1.6 2.1 2.5 v r remote remote feedback switch resistance 2v < v remote < v cc l 15 30 i sctmr(up) short-circuit timer pull-up current v sctmr = 1v l C35 C50 C65 a i sctmr(dn) short-circuit timer pull-down current v sctmr = 1v l 123 a v sctmr(th) short-circuit timer threshold voltage l 1.1 1.23 1.4 v i sdtmr(up) shutdown timer pull-up current v sdtmr = 1v l C7 C10 C13 a v sdtmr(th) shutdown timer threshold voltage l 1.1 1.23 1.4 v i pgi(up) power good input pull-up current v pgi = 0v l C5 C10 C15 a v pgi(th) power good input threshold voltage l 0.8 1.4 v i pgtmr(up) power good timer pull-up current v pgtmr = 1v l C8 C10 C14 a v pgtmr(th) power good timer threshold voltage l 1.1 1.23 1.4 v
ltc2925 4 2925fc typical performance characteristics i cc vs v cc v gate vs v cc v gate vs i gate i gate fast pull-down vs temperature v rampbuf(ol) vs temperature electrical characteristics note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into the device pins are positive; all currents out of device pins are negative. all voltages are referenced to ground unless otherwise speci? ed. note 3: the gate pin is internally limited to a minimum of 11.5v. driving this pin to voltages beyond the clamp may damage the part. 2.5 i cc (ma) 12 10 8 6 4 2 0 3 3.5 4 4.5 2925 g01 v cc (v) 5 5.5 i trackx = i fbx = 1ma i rampbuf = 3ma i trackx = i fbx = 0ma i rampbuf = 0ma v cc (v) 2 8 v gate (v) 9 10 12 11 34 2925 g02 56 i gate (a) 0 0 v gate (v) 5 10 15 510 v cc = 2.9v v cc = 5.5v 2925 g03 15 temperature (c) C50 C25 i gate (ma) 50 75 2925 g04 0 25 100 50 45 40 35 30 25 v cc = 5.5v v cc = 2.9v v gate = 5v temperature (c) C50 v rampbuf(ol) (mv) 25 75 2925 g05 C25 0 50 70 65 60 55 50 45 40 35 30 100 v cc = 2.9v v cc = 5.5v v rampbuf(oh) vs temperature temperature (c) C50 80 90 100 25 75 2925 g06 70 60 C25 0 50 100 50 40 v rampbuf(oh) (mv) 110 v cc = 2.9v v cc = 5.5v speci? cations are at t a = 25c
ltc2925 5 2925fc typical performance characteristics speci? cations are at t a = 25c v sdx (ol) vs v cc v track vs temperature tracking cell error vs i trackx v cc (v) 0 0 v sdx (ol) (v) 0.2 0.4 0.6 0.8 1.0 1 234 2925 g07 5 i sdx = 10a i sdx = 5ma temperature (c) C50 v trackx (v) 0.805 0.800 0.795 0.790 050 C25 25 75 2925 g08 100 v cc = 5.5v i trackx = 10a v cc = 2.9v i trackx = 1ma v cc = 5.5v i trackx = 1ma v cc = 2.9v i trackx = 10a i trackx (ma) 0 3 4 5 4 2925 g09 2 1 0 123 0.5 4.5 1.5 2.5 3.5 5 ? v trackx 0.8v i fbx i trackx C1 (%) pin functions gn/uf packages v cc (pin 1/pin 22): positive supply input. the operating supply input range is 2.9v to 5.5v. an undervoltage lockout circuit resets the part when the supply is below 2.5v. v cc should be bypassed to gnd with a 0.1f capacitor. sensep (pin 2/pin 23): circuit breaker positive sense input. sensep and sensen measure the voltage across the sense resistor and trigger the circuit breaker function when the current exceeds the level programmed by the sense resistor for longer than a short-circuit timer cycle (see sctmr). if unused, tie sensen and sensep to v cc . sensen (pin 3/pin 24): circuit breaker negative sense input. sensen connects to the low side of the current sense resistor. sensep and sensen monitor the current through the external fet by measuring the voltage across the sense resistor. the circuit breaker turns off the fet when the sense voltage exceeds 50mv for longer than a short circuit timer cycle (see sctmr). if the short-circuit timer times out, the gate pin will be pulled low im- mediately to protect the fet. if unused, tie sensen and sensep to v cc . on (pin 4/pin 1): on control input. the on pin has a threshold of 1.23v with 75mv of hysteresis. an active high will cause 10a to ? ow from the gate pin, ramping up the supplies. an active low pulls 10a from the gate pin, ramp- ing the supplies down. pulling the on pin below 0.4v resets the electronic circuit breaker in the ltc2925. if a resistive divider connected to v cc drives the on pin, the supplies will automatically start up when v cc is fully powered. sdtmr (pin 5/pin 2): shutdown timer. a capacitor from sdtmr to gnd sets the delay time between the on pin tran- sitioning high (which releases the sdx pins) and the supplies beginning to ramp-up. float sdtmr when it is unused. sd1 , sd2 , sd3 (pins 6, 7, 8/pins 3, 4, 5): outputs for slave supply shutdowns. the sdx pins are open-drain outputs that hold the shutdown (run/ss) pins of the slave supplies low until the on pin is pulled above 1.23v. the sdx pins will be pulled low again when ramp <100mv and on <1.23v. if a slave supply is capable of operating with an input supply that is lower than the ltc2925s minimum operating voltage of 2.9v, the sdx pins can be used to hold off the slave supplies. each sdx pin is capable of sinking greater than 1ma with supplies as low as 2.3v. rampbuf (pin 9/pin 6): ramp buffer output. provides a low impedance buffered version of the signal on the ramp pin. this buffered output drives the resistive dividers that connect to the trackx pins. limit the capacitance at the rampbuf pin to less than 100pf. gnd (pin 10/pins 7, 25): circuit ground. track1, track2, track3 (pins 15, 14, 12/pins 12, 11, 9): tracking control input pin. a resistive divider between rampbuf, trackx and gnd determines the tracking
ltc2925 6 2925fc pin functions gn/uf packages pro? le of outx (see applications information). trackx pulls up to 0.8v and the current supplied at trackx is mirrored at fbx. the trackx pin is capable of supply- ing at least 1ma when v cc = 2.9v. it may be capable of supplying up to 30ma when the supply is at 5.5v, so care should be taken not to short this pin for extended periods. limit the capacitance at the trackx pin to less than 25pf. float the trackx pins if unused. fb1, fb2, fb3 (pins 16, 13, 11/pins 13, 10, 8): feed- back control output. fbx connects to the feedback node of slave supplies. tracking is achieved by mirroring the current from trackx into fbx. if the appropriate resistive divider connects rampbuf and trackx, the fbx current will force outx to track ramp . the ltc2925 is capable of controlling slave supplies with feedback voltages between 0v and 1.6v. to prevent damage to the slave supply, the fbx pin will not force the slaves feedback node above 2.5v. in addition, it will not actively sink current from this node even when the ltc2925 is unpowered. float the fbx pins if unused. remote (pin 17/pin 14): remote sense switch. a 15 switch connects remote to ramp when the gate is fully enhanced (gate > ramp + 4.9v). otherwise, it presents a high impedance. when the slave supplies track the master supply, remote can be used to compensate for the voltage drop across the external sense resistor and n-channel fet. a resistor between the output and the sense nodes of the master supply provides feedback before the external fet is fully enhanced. if an external fet is not used, ? oat remote. ramp (pin 18/pin15): ramp buffer input. when the ramp pin is connected to the source of the external n-channel fet, the slave supplies track the fets source as it ramps up and down. alternatively, when no external fet is used, the ramp pin can be tied directly to the gate pin. in this con? guration, the supplies track the capacitor on the gate pin as it is charged and discharged by the 10a current source controlled by the on pin. when the gate is fully enhanced (gate > ramp + 4.9v) the open-drain status pin goes high impedance and the remote sense switch connects the ramp pin to the remote pin. gate (pin 19/pin 16): gate drive for external n-channel fet. when the on pin is high, an internal 10a current source charges the gate of the external n-channel mosfet. a capacitor connected from gate to gnd sets the ramp rate. it is a good practice to add a 10 resistor between this capacitor and the fets gate to prevent high frequency fet oscillations. an internal charge pump guarantees that gate will pull up to 5v above v cc ensuring that logic-level n-channel fets are fully enhanced. when the on pin is pulled low, the gate pin is pulled to gnd with a 10a current source. under a short-circuit condition, the elec- tronic circuit breaker in the ltc2925 pulls the gate low immediately with 20ma. tie gate to gnd if unused. fault (pin 20/pin 17): circuit breaker and power good timer fault output. fault is an open-drain output that pulls low when the electronic circuit breaker is activated or a power good timeout fault is detected. fault is reset by pulling on below 0.4v. to allow retry, tie fault to on. status (pin 21/pin 18): power good status indicator. the status pin is an open-drain output that pulls low until gate has been fully charged at which time all supplies will have reached their ? nal operating voltage. pgi (pin 22/pin 19): power good timer input. pgi con- nects to the rst pin of the downstream supply monitor. if pgi has not transitioned high within a power good timer cycle (see pgtmr), the fault pin will be pulled low and the supplies will be turned off by pulling the gate pin low with 20ma. pgi is pulled up with 10a. an internal schottky diode allows pgi to be pulled safely above v cc . float pgi when it is unused. pgtmr (pin 23/pin 20): power good timer. a capacitor from pgtmr to gnd sets the power good timer duration. while on > 1.23v, the pgtmr pin will pull up to v cc with 10a. otherwise, it pulls to gnd. if the voltage on the pgtmr pin exceeds 1.23v and pgi is still low, fault will be pulled low and the gate will be pulled to ground with 20ma until the power good timer fault is cleared by pull- ing on below 0.4v. if fault is tied back to on the system will automatically retry after a fault . in this mode, verify that the slave supplies current limits provide suf? cient protection under short-circuit conditions. tie pgtmr to gnd when it is unused.
ltc2925 7 2925fc sctmr (pin 24/pin 21): circuit breaker timer. a capacitor from sctmr to gnd programs the maximum time that a short circuit can be sustained before gate is pulled low. when (sensep C sensen) > 50mv, sctmr will pull up with 50a, otherwise it pulls down with 2a. when the voltage at sctmr exceeds 1.23v, the gate will be pulled to ground with 20ma and the fault pin will be pulled low. the circuit breaker function is reset by pulling on below 0.4v. the gate pin will not rise again until sctmr has been pulled below 100mv by the 2a current source. if fault is tied back to on the system will automatically retry after a fault. tie sctmr to gnd if the circuit breaker is not used. pin functions gn/uf packages block diagram pin numbers in parentheses are for the uf package. 10a 10a v cc 2.6v 0.1v + C C + rampbuf fb3 track3 gnd 2925 fbd 1 v cc 10 12 9 (6) remote 17 (14) status 1 11 fb2 track2 14 13 fb1 track1 0.8v v cc + C 15 16 + C 10a charge pump s q 0.1v r sctmr on 4 (1) pgtmr 10a 23 pgi 22 sctmr 24 sdx (15) fault (17) (22) (7, 25) 20 sensen (24) 3 sensep (23) 2 sdtmr (2) 5 gate (16) 19 ramp 18 v cc 1.2v gate gate > ramp + 4.9v C + 4.9v 1.2v + C 0.4v + C onsig C + 1.2v 1.2v C + sq r 2a 50a C + 50mv sensep > sensen + 50mv (8) (10) (13) (9) (11) (12) (20) (19) (21) v cc v cc v cc 21 (18)
ltc2925 8 2925fc applications information power supply tracking and sequencing the ltc2925 handles a variety of power-up pro? les to satisfy the requirements of digital logic circuits including fpgas, plds, dsps and microprocessors. these require- ments fall into one of the four general categories illustrated in figures 1 to 4. some applications require that the potential difference between two power supplies must never exceed a speci- ? ed voltage. this requirement applies during power-up and power-down as well as during steady-state operation, often to prevent destructive latch-up in a dual supply ic. typically, this is achieved by ramping the supplies up and down together (figure 1). in other applications it is desir- able to have the supplies ramp up and down with ? xed voltage offsets between them (figure 2) or to have them ramp up and down ratiometrically (figure 3). certain applications require one supply to come up after another. for example, a system clock may need to start before a block of logic. in this case, the supplies are sequenced as in figure 4 where the 1.8v supply ramps up completely followed by the 2.5v supply and then the 1.5v supply. operation the ltc2925 provides a simple solution to all of the power supply tracking and sequencing pro? les shown in figures 1 to 4. a single ltc2925 controls up to four supplies with three slave supplies that track a master signal. with just two resistors, a slave supply is con? gured to ramp up as a function of the master signal. this master signal can be a fourth supply that is ramped up through an external fet, whose ramp rate is set with a single capacitor, or it can be a signal generated by tying the gate and ramp pins to an external capacitor. 1v/div master slave1 slave2 slave3 10ms/div 2925 f01 1v/div master slave1 slave2 slave3 10ms/div 2925 f02 2v/div master slave1 slave2 slave3 10ms/div 2925 f03 2v/div slave1 slave2 slave3 10ms/div 2925 f04 figure 1. coincident tracking figure 2. offset tracking figure 3. ratiometric tracking figure 4. supply sequencing
ltc2925 9 2925fc applications information tracking cell the ltc2925s operation is based on the tracking cell shown in figure 5, which uses a proprietary wide-range current mirror. the tracking cell shown in figure 5 servos the track pin at 0.8v. the current supplied by the track pin is mirrored at the fb pin to establish a voltage at the output of the slave supply. the slave output voltage varies with the master signal, enabling the slave supply to be controlled as a function of the master signal with terms set by r ta and r tb . by selecting appropriate values of r ta and r tb , it is possible to generate any of the pro? les in figures 1 to 4. in a properly designed system, when the master signal has reached its maximum voltage the current from the track1 pin is zero. in this case, there is no current from the fb1 pin and the ltc2925 has no effect on the output voltage accuracy, transient response or stability of the slave supply. when the on pin falls below v on(th) C v on(hyst) , typi- cally 1.225v, the gate pin pulls down with 10a and the master signal and the slave supplies will fall at the same rate as they rose previously. the on pin can be controlled by a digital i/o pin or it can be used to monitor an input supply. by connecting a resistive divider from an input supply to the on pin, the supplies will ramp up only after the monitored supply has reached a preset voltage. C + r ta r tb fb track master 0.8v v cc r fa 2925 f05 slave r fb dc/dc + C fb out figure 5. simpli? ed tracking cell controlling the ramp-up and ramp-down behavior the operation of the ltc2925 is most easily understood by referring to the simpli? ed functional diagram in figure 6. when the on pin is low, the gate pin is pulled to ground causing the master signal to remain low. since the current through r tb1 is at its maximum when the master signal is low, the current from fb1 is also at its maximum. this cur- rent drives the slaves output to its minimum voltage. when the on pin rises above 1.23v, the master signal rises and the slave supply tracks the master signal. the ramp rate is set by an external capacitor driven by a 10a current source from an internal charge pump. if no external fet is used, the ramp rate is set by tying the ramp and gate pins together at one terminal of the external capacitor (see the ratiometric tracking example). 1.2v C + C + C + gate q1 master slave1 c gate 1.2v on rampbuf 10a v cc v cc r onb r ona r ta1 r tb1 10a 50a 2a ramp fb1 track1 0.8v r fa1 r fb1 dc/dc 2925 f06 1 s 50mv sensen sensep sensep C sensen > 50mv sctmr figure 6. simpli? ed functional block diagram
ltc2925 10 2925fc optional external fet figure 7 illustrates how an optional external n-channel fet can ramp up a single supply that becomes the mas- ter signal. when used, the fets gate is tied to the gate pin and its source is tied to the ramp pin. under normal operation, the gate pin sources or sinks 10a to ramp the fets gate up or down at a rate set by the external capacitor connected to the gate pin. the series fet easily controls any supply with an output voltage between 0v and v cc . see the typical applications section for examples. the short-circuit timer duration is con? gured by a capaci- tor tied between sctmr and gnd. sctmr will pull up with 50a when sensep C sensen > 50mv. otherwise, it pulls down with 2a. when the voltage at sctmr exceeds 1.23v, the gate will be pulled to ground with 20ma and the fault pin will be pulled low. thus, the capacitor, c sctmr , required to con? gure the short-circuit timer duration, t sctmr is determined from: c at v sctmr sctmr = 50 123 ? . because the slave supplies track the ramp pin which is driven by the external fet, they are pulled low by the track- ing circuit when a short-circuit fault occurs. following a short-circuit fault, the fet is latched off and fault is pulled low until the fault is cleared by pulling the on pin below 0.4v. note that the supplies will not be allowed to ramp up again until sctmr has been pulled below about 100mv by the 2a pull-down current source. the electronic circuit breaker supports any supply voltage between 0v and v cc . although it is normally used to monitor current through the optional series fet, it is capable of monitoring other currents, including the current from a slave supply. the typical applications section shows one such example. if the electronic circuit breaker is not used, tie sensep and sensen to v cc and sctmr to gnd. power good timeout the power good timeout circuit turns off the supplies if an external supply monitor, connected to the pgi pin, fails to indicate that all supplies have entered regulation in time after power up begins. after power up is complete, it turns off the supplies if any supply exits regulation. the power good timer duration is con? gured by a capaci- tor tied between pgtmr and gnd. pgtmr will pull up the cpgtmr capacitor with 10a starting when the on pin is driven above 1.23v. once the voltage at the pgtmr exceeds 1.23v, a fault will trip if the pgi pin is low. when the power good timeout circuit detects a fault, the gate applications information r sense q1 0.1f c pgtmr 10k v cc sensep sensen 3.3v v in 3.3v r onb v in r tb1 r tb2 r fa2 2.5v slave2 master r fb2 r ta2 r tb3 r ta3 r ta1 r ona rampbuf track1 track2 track3 fb2 gate ltc2925 pgtmr c sdtmr sdtmr c sctmr sctmr gnd 2925 f07 ramp r fa3 1.5v slave3 r fb3 dc/dc in fb = 0.8v out dc/dc in fb = 0.8v run/ss run/ss out fb3 3.3v pgi r fa1 1.8v slave1 r fb1 supply monitor dc/dc in fb = 1.235v run/ss out fb1 fault on 10k v in status remote rst sd3 sd2 sd1 c gate 10 figure 7. typical application with external fet electronic circuit breaker the ltc2925 features an electronic circuit breaker function that protects the optional series fet against short circuits. an external sense resistor is used to measure the current ? owing in the fet. if the voltage across the sense resistor exceeds 50mv for more than a short-circuit timer cycle, the gate of the fet is pulled low with 20ma, turning it off.
ltc2925 11 2925fc pin is pulled low, the supplies are latched off, and the fault pin is held low until the fault is cleared by taking the on pin below 0.4v. the pgi pin, which is normally connected to the rst pin of an external supply monitor, is pulled up with 10a through a schottky diode allowing it to be pulled safely above v cc . since, pgtmr pulls up with a 10a current source, the capacitor, c pgtmr , required to con? gure the power good timeout duration, t pgtmr , is determined from: c a t v pgtmr pgtmr = 10 123 ? . if the power good timeout circuit is unused, tie pgtmr low and ? oat pgi. the ramp buffer the rampbuf pin provides a buffered version of the ramp pin voltage that drives the resistive dividers on the trackx pins. when there is no external fet, it provides up to 3ma to drive the resistors even though the gate pin only supplies 10a (figure 8). the rampbuf pin also proves useful in systems with an external fet. since the track cell drives 0.8v on the trackx pins, if r tbx is connected directly to the fets source, the trackx pin could potentially pull up the fets source towards 0.8v when the fet is off. rampbuf blocks this path. shutdown outputs in some applications it might be necessary to control the shutdown or run/ss pins of the slave supplies. the ltc2925 may not be able to supply the rated 1ma of current from the fb1, fb2, and fb3 pins when v cc is below 2.9v. if the slave power supplies are capable of operating at low input voltages, use the open-drain sdx outputs to drive the shdn or run/ss pins of the slave supplies (figures 7 and 8). the sdx pins are released when the on pin rises above 1.23v, v cc is above the 2.6v undervoltage lockout condition, and there are no faults latched. the shutdown timer begins at the same time, and the supplies begin to ramp up after the shutdown timer cycle completes. the duration of the timer cycle is con? gured by a capacitor tied between sdtmr and gnd. the capacitor voltage is ramped up by a 10a current source and the sdtmr cycle completes when its voltage reaches 1.23v. thus, the capacitor, c sdtmr , required for a given shutdown timer cycle, t sdtmr , is determined from: c a t v sdtmr sdtmr = 10 123 ? . the sdx pins pull low again when the on pin is pulled below 1.23v and the ramp pin is below about 100mv. applications information c gate 0.1f c pgtmr v cc sensep sensen v in v in v in r onb v in r tb1 r tb2 r fa2 slave2 r fb2 r ta2 r tb3 r ta3 r ta1 r ona rampbuf track1 track2 track3 fb2 gate ltc2925 pgtmr c sdtmr sdtmr sctmr gnd 2925 f08 ramp r fa3 slave3 r fb3 dc/dc in fb out dc/dc in fb run/ss run/ss out fb3 v in pgi r fa1 slave1 r fb1 supply monitor dc/dc in fb run/ss out fb1 fault on v in status remote rst sd3 sd2 sd1 figure 8. typical application without external fet
ltc2925 12 2925fc status output the status pin provides an indication that the supplies are ? nished ramping up. this pin is an open-drain output that pulls low until the gate has been fully charged. since the gate pin drives the gate of the external fet, or the ramp pin directly when no fet is used, the supplies are completely ramped up when the gate pin is fully charged. the status pin will go low again when the gate pin is pulled low, either because of a short-circuit fault, a power good timeout fault, or because the on pin has been pulled low. fault output the fault pin is an open-drain output that pulls low when the electronic circuit breaker is activated due to a short-circuit or power good timeout fault. fault is reset by pulling on below 0.4v. the supplies will not be allowed to ramp up again until the sctmr, pgtmr and sdtmr pins are below about 100mv, and the on pin is pulled above 1.23v. retry on fault the ltc2925 continuously attempts to ramp up the outputs after a fault if the fault pin is tied to the on pin (figure 9). if a short-circuit fault occurs in this con? guration, the sctmr pin ramps up the c sctmr capacitor with 50a until it reaches 1.23v. then, gate is pulled low turning off the shorted fet. at the same time, the fault pins open-drain output pulls on low. the c sctmr capacitor is pulled down with 2a until it reaches about 100mv. after the c sctmr capacitor reaches 100mv, the shutdown timer begins and upon completing a shutdown timer cycle, the supplies start ramping up again. if there is no short-circuit this time, the supplies will come up normally. otherwise the retry cycle will repeat. if a longer off time is required between retry attempts, the c sdtmr capacitor value can be increased, providing a greater delay before the fets gate ramps up on each cycle. note that tying fault to on also causes the ltc2925 to retry on power good timeout faults. in this mode, verify that the slave supplies current limits provide suf? cient protection under short-circuit conditions. applications information r sense q1 0.1f c pgtmr v cc sensep sensen v in v in r onb v in r tb1 r tb2 r fa2 slave2 master r fb2 r ta2 r tb3 r ta3 r ta1 r ona rampbuf track1 track2 track3 fb2 gate ltc2925 pgtmr c sdtmr sdtmr c sctmr sctmr gnd 2925 f09 ramp r fa3 slave3 r fb3 dc/dc in fb out dc/dc in fb run/ss run/ss out fb3 v in pgi r fa1 slave1 r fb1 supply monitor dc/dc in fb run/ss out fb1 fault on 10k v in status remote rst sd3 sd2 sd1 c gate 10 figure 9. retry on fault
ltc2925 13 2925fc 3-step design procedure the following 3-step design procedure allows one to choose the track resistors, r tax and r tbx , and the gate capacitor, c gate , that give any of the tracking or sequencing pro? les shown in figures 1 to 4. a basic four supply application circuit is shown in figure 10. 1. set the ramp rate of the master signal. solve for the value of c gate , the capacitor on the gate pin, based on the desired ramp rate (v/s) of the master supply, s m : c i s where i a gate gate m gate = 10 1 () if the external fet has a gate capacitance comparable to c gate , then the external capacitors value should be reduced to compensate for the fets gate capacitance. if no external fet is used, tie the gate and ramp pins together, connect sensen and sensep to v cc , and con- nect sctmr to gnd. 2. solve for the pair of resistors that provide the desired ramp rate of the slave supply, assuming no delay. choose a ramp rate for the slave supply, s s . if the slave supply ramps up coincident with the master supply or with a ? xed voltage offset, then the ramp rate equals the master supplys ramp rate. be sure to use a fast enough ramp rate for the slave supply so that it will ? nish ramping before the master supply has reached its ? nal supply value. if not, the slave supply will be held below the intended regulation value by the master supply. use the following formulas to determine the resistor values for the desired ramp rate, where r fb and r fa are the feedback resistors in the slave supply and v fb is the feedback reference voltage of the slave supply: rr s s tb fb m s = ?() 2 r v v r v r v r ta track fb fb fb fa track tb = + ? () 3 where v track 0.8v. note that large ratios of slave ramp rate to master ramp rate, s s /s m , may result in negative values for r ta . if a suf? ciently large delay is used in step 3, r ta will be posi- tive, otherwise s s /s m must be reduced. 3. choose r ta to obtain the desired delay. if no delay is required, such as in coincident and ratio- metric tracking, then simply set r ta = r ta . if a delay is desired, as in offset tracking and supply sequencing, calculate r ta to determine the value of r ta where t d is the desired delay. r vr ts ta track tb dm = ? ? () 4 rrr ta ta ta = || ( ) 5 the parallel combination of r ta and r ta . as noted in step 2, small delays and large ratios of slave ramp rate to master ramp rate (usually only seen in se- quencing) may result in solutions with negative values for r ta . in such cases, either the delay must be increased or the ratio of slave ramp rate to master ramp rate must be reduced. applications information r sense q1 0.1f 10k v cc sensep sensen v in v in v in r onb 138k v in r tb1 r tb2 r fa2 slave2 master r fb2 r ta2 r tb3 r ta3 r ta1 r ona 100k rampbuf track1 track2 track3 fb2 gate ltc2925 pgtmr sdtmr sctmr gnd 2925 f10 ramp r fa3 slave3 r fb3 dc/dc in fb out dc/dc in fb run/ss run/ss out fb3 v in pgi r fa1 slave1 r fb1 supply monitor dc/dc in fb run/ss out fb1 fault on 10k v in status remote rst sd3 sd2 sd1 c gate 10 figure 10. four supply application
ltc2925 14 2925fc applications information coincident tracking example a typical four supply application is shown in figure 12. the master signal is a 3.3v module. the slave 1 supply is a 1.8v switching power supply, the slave 2 supply is a 2.5v switching power supply, and the slave 3 supply is a 1.5v supply. all three slave supplies track coincidently with the 3.3v supply that is controlled with an external fet. the ramp rate of the supplies is 100v/s. the 3-step design procedure detailed previously can be used to determine component values. only the slave 1 supply is considered here as the procedure is the same for the other supplies. 1. set the ramp rate of the master signal. from equation 1: c a vs f gate == 10 100 01 / . 2. solve for the pair of resistors that provide the desired slave supply behavior, assuming no delay. from equation 2: rk vs vs k tb == 16 5 100 100 16 5 .? / / . from equation 3: r v v k v k v k k ta = + 08 1 235 16 5 1 235 35 7 08 16 5 13 . . . . . ? . . 3. choose rta to obtain the desired delay. since no delay is desired, r ta = r ta . master slave2 slave1 1v/div 1v/div slave3 10ms/div 10ms/div 2925 f11 figure 11. coincident tracking from figure 12 0.015 q1 si4412ady 0.1f c pgtmr 0.82f 10k v cc sensep sensen 3.3v v in 3.3v r onb 138k 3.3v v in r tb1 16.5k r tb2 88.7k r fa2 41.2k 2.5v slave2 master r fb2 88.7k r ta2 41.2k r tb3 86.6k r ta3 100k r ta1 13k r ona 100k rampbuf track1 track2 track3 fb2 gate ltc2925 pgtmr c sdtmr 0.082f sdtmr c sctmr 0.47f sctmr gnd 2925 f12 ramp r fa3 100k 1.5v slave3 r fb3 86.6k dc/dc in fb = 0.8v out dc/dc in fb = 0.8v run/ss run/ss out fb3 3.3v pgi r fa1 35.7k 1.8v slave1 r fb1 16.5k supply monitor dc/dc in fb = 1.235v run/ss out fb1 fault on 10k v in status remote rst sd3 sd2 sd1 c gate 0.1f 10 in this example, all supplies remain low while the on pin is held below 1.23v. when the on pin rises above 1.23v, 10a pulls up cgate and the gate of the fet at 100v/s. as the gate of the fet rises, the source follows and pulls up the output to 3.3v at 100v/s. this output serves as the master signal and is buffered from the ramp pin to the rampbuf pin. as this output and the rampbuf pin rise, the current from the trackx pins is reduced. consequently, the voltages at the slave supplies outputs increase, and the slave supplies track the master supply. when the on pin is again pulled below 1.23v, 10a will pull down c gate and the gate of the fet at 100v/s. if the loads on the outputs are suf? cient, all outputs will track down coincidently at 100v/s. figure 12. coincident tracking example
ltc2925 15 2925fc applications information ratiometric tracking example this example converts the coincident tracking example to the ratiometric tracking pro? le shown in figure 13, using three supplies without an external fet. the ramp rate of the master signal remains unchanged (step 1) and there is no delay in ratiometric tracking (step 3), so only the result of step 2 in the 3-step design procedure needs to be considered. in this example, the ramp rate of the 1.8v slave 1 supply ramps up at 60v/s, the 2.5v slave 2 supply ramps up at 85v/s, and the 1.5v slave 3 supply ramps up at 50v/s. always verify that the chosen ramp rate will al- low the supplies to ramp-up completely before rampbuf reaches v cc . if the 1.8v supply were to ramp-up at 50v/s it would only reach 1.65v because the rampbuf signal would reach its ? nal value of v cc = 3.3v before the slave supply reached 1.8v. 2. solve for the pair of resistors that provide the desired slave supply behavior, assuming no delay. from equation 2: rk vs vs k tb =? 16 5 100 60 27 4 . / / . figure 13. ratiometric tracking from figure 14 slave2 slave1 1v/div 1v/div slave3 10ms/div 10ms/div 2925 f13 0.1f c pgtmr 0.82f 10k v cc sensep sensen 3.3v v in 3.3v r onb 138k r tb1 27.4k r tb2 100k r fa2 41.2k 2.5v slave2 r fb2 88.7k r ta2 38.3k r tb3 174k r ta3 63.4k r ta1 10k r ona 100k rampbuf track1 track2 track3 fb2 ltc2925 pgtmr c sdtmr 0.082f sdtmr c sctmr 0.41f sctmr gnd 2925 f14 r fa3 100k 1.5v slave3 r fb3 86.6k dc/dc in fb = 0.8v out dc/dc in fb = 0.8v run/ss run/ss out fb3 3.3v pgi r fa1 35.7k 1.8v slave1 r fb1 16.5k supply monitor dc/dc in fb = 1.235v run/ss out fb1 fault on 10k v in status remote rst c gate 0.1f 3.3v v in gate ramp sd3 sd2 sd1 figure 14. ratiometric tracking example from equation 3: r v v k v k v k k ta = + 08 1 235 16 5 1 235 35 7 08 27 5 10 . . . . . ? . . step 3 is unnecessary because there is no delay, so r ta = r ta .
ltc2925 16 2925fc applications information offset tracking example converting the circuit in the coincident tracking example to the offset tracking shown in figure 15 is relatively simple. here the 1.8v slave 1 supply ramps up 1v below the master. the ramp rate remains the same (100v/s), so there are no changes necessary to steps 1 and 2 of the 3-step design procedure. only step 3 must be considered. be sure to verify that the chosen voltage offsets will allow the slave supplies to ramp up completely. in this example, if the voltage offset were 2v, the slave supply would only ramp up to 3.3v C 2v = 1.3v. 3. choose r ta to obtain the desired delay. first, convert the desired voltage offset, v os , to a delay, t d , using the ramp rate: t v s v vs ms d os s == = 1 100 10 6 / () from equation 4: r vk ms v s k ta == 08 165 1 100 13 2 .?. ?/ . from equation 5: rkkk ta = 131 132 665 .||. . 0.015 q1 si4412ady 0.1f c pgtmr 0.82f 10k v cc sensep sensen 3.3v v in 3.3v r onb 138k 3.3v v in r tb1 16.5k r tb2 88.7k r fa2 41.2k 2.5v slave2 master r fb2 88.7k r ta2 31.6k r tb3 86.6k r ta3 31.6k r ta1 6.65k r ona 100k rampbuf track1 track2 track3 fb2 gate ltc2925 pgtmr c sdtmr 0.082f sdtmr c sctmr 0.41f sctmr gnd 2925 f16 ramp r fa3 100k 1.5v slave3 r fb3 86.6k dc/dc in fb = 0.8v out dc/dc in fb = 0.8v run/ss run/ss out fb3 3.3v pgi r fa1 35.7k 1.8v slave1 r fb1 16.5k supply monitor dc/dc in fb = 1.235v run/ss out fb1 fault on 10k v in status remote rst sd3 sd2 sd1 c gate 0.1f 10 slave2 master slave1 1v/div 1v/div slave3 10ms/div 10ms/div 2925 f15 figure 15. offset tracking from figure 16 figure 16. offset tracking example
ltc2925 17 2925fc applications information supply sequencing example in figure 17, the three slave supplies are sequenced in- stead of tracking. as in the coincident tracking example, the 3.3v master supply ramps up at 100v/s through an external fet, so step 1 remains the same. the 1.8v slave 1 supply ramps up at 1000v/s beginning 10ms after the master signal starts to ramp up. the 2.5v slave 2 supply ramps up at 1000v/s beginning 20ms after the master signal begins to ramp up. the 1.5v slave 3 supply ramps up at 1000v/s beginning 25ms after the master signal begins to ramp up. note that not every combination of ramp rates and delays is possible. small delays and large ratios of slave ramp rate to master ramp rate may result in solutions that require negative resistors. in such cases, either the delay must be increased or the ratio of slave ramp rate to master ramp rate must be reduced. in this example, solving for the slave 1 supply yields: 2. solve for the pair of resistors that provide the desired slave supply behavior, assuming no delay. from equation 2: rk vs vs k tb =? 16 5 100 1000 165 . / / . from equation 3: r v v k v k v k k ta = + 08 1 235 16 5 1 235 35 7 08 165 213 . . . . . ? . . ?. slave2 master slave1 1v/div 1v/div slave3 10ms/div 10ms/div 2925 f17 figure 17. supply sequencing from figure 18 3. choose r ta to obtain the desired delay. from equation 4: r vk ms v s k ta == 08 165 10 100 132 .?. ?/ . from equation 5: rkkk ta = ?. || . . 213 132 348 0.015 q1 si4412ady 0.1f c pgtmr 0.82f 10k v cc sensep sensen 3.3v v in 3.3v r onb 138k 3.3v v in r tb1 1.65k r tb2 8.87k r fa2 41.2k 2.5v slave2 master r fb2 88.7k r ta2 4.87k r tb3 8.66k r ta3 3.74k r ta1 3.48k r ona 100k rampbuf track1 track2 track3 fb2 gate ltc2925 pgtmr c sdtmr 0.082f sdtmr c sctmr 0.41f sctmr gnd 2925 f18 ramp r fa3 100k 1.5v slave3 r fb3 86.6k dc/dc in fb = 0.8v out dc/dc in fb = 0.8v run/ss run/ss out fb3 3.3v pgi r fa1 35.7k 1.8v slave1 r fb1 16.5k supply monitor dc/dc in fb = 1.235v run/ss out fb1 fault on 10k v in status remote rst sd3 sd2 sd1 c gate 0.1f 10 figure 18. supply sequencing example
ltc2925 18 2925fc applications information final sanity checks the collection of equations below is useful for identifying unrealizable solutions. as stated in step 2, the slave supply must ? nish ramping before the master signal has reached its ? nal voltage. this can be veri? ed by the following equation: v r r v track tb ta master 1 +
< here, v track = 0.8v. v master is the ? nal voltage of the mas- ter signal, either the supply voltage ramped up through the optional external fet or v cc when no fet is present. it is possible to choose resistor values that require the ltc2925 to supply more current than the electrical char- acteristics table guarantees. to avoid this condition, check that i trackx does not exceed 1ma and i rampbuf does not exceed 3ma. to con? rm that i trackx < 1ma, the trackx pin(s) maxi- mum guaranteed current, verify that: v rr ma track ta tb < 1 finally, check that the rampbuf pin will not be forced to sink more than 3ma when it is at 0v or be forced to source more than 3ma when it is at v master . v r v r v r 3ma and v rr v rr v rr 3ma track tb1 track tb2 track tb3 master ta1 tb1 master ta2 tb2 master ta3 tb3 ++< + + + + + < caution with boost regulators and linear regulators note that the ltc2925s tracking cell is not able to control the outputs of all types of power supplies. if it is necessary to control a supply, where the output is not controllable through its feedback node, the series fet can be used to control its output. for example, boost regulators commonly contain an inductor and diode between the input supply and the output supply providing a dc current path when the output voltage falls below the input voltage. therefore, the ltc2925s tracking cell will not effectively drive the supplys output below the input. special caution should be taken when considering the use of linear regulators. three-terminal linear regulators have a reference voltage that is referred to the output supply rather than to ground. in this case, driving current into the regulators feedback node will cause its output to rise rather than fall. even linear regulators that have their ref- erence voltage referred to ground, including low-dropout regulators (ldos), may be problematic. linear regulators commonly contain circuitry that prevents driving their outputs below their reference voltage. this may not be obvious from the datasheets, so lab testing is recom- mended whenever the ltc2925s tracking cell is used to control linear regulators.
ltc2925 19 2925fc applications information load requirements when the supplies are ramped down quickly, either the load or the supply itself must be capable of sinking enough current to support the ramp rate. for example, if there is a large output capacitance on the supply and a weak resistive load, supplies that do not sink current will have their falling ramp rate limited by the rc time constant of the load and the output capacitance. figure 19 shows the case when the 2.5v supply does not track the 1.8v and 3.3v supplies near ground. start-up delays often power supplies do not start-up immediatley when their input supplies are applied. if the ltc2925 tries to ramp-up these power supplies as soon as the input sup- ply is present, the start-up of the outputs may be delayed defeating the tracking circuit (figure 20). often this delay is intentionally con? gured by a soft-start capacacitor. this can be remedied either by reducing the soft-start capacitor on the slave supply or by increasing the shutdown timer cycle con? gured by c sdtmr . 1v/div master slave2 slave1 1ms/div 2925 f19 1v/div master slave1 slave2 1ms/div 2925 f20 on figure 19. weak resistive load figure 20. power supply start-ups delayed
ltc2925 20 2925fc applications information layout considerations be sure to place a 0.1f bypass capacitor as near as pos- sible to the supply pin of the ltc2925. to minimize the noise on the slave supplies outputs, keep the traces connecting the fbx pins of the ltc2925 and the feedback nodes of the slave supplies as short as possible. in addition, do not route those traces next to signals with fast transition times. in some circumstances it might be advantageous to add a resistor near the feed- back node of the slave supply in series with the fbx pin of the ltc2925. this resistor must not exceed: r vv i v v rr series fb max fb fa f == 16 16 1 .C . C|| b b () this resistor is most effective if there is already a capacitor at the feedback node of the slave supply (often a compensation component). increasing the capacitance on a slave supplys feedback node will further improve the noise immunity, but could affect the stability and transient response of the supply. for proper circuit breaker operation, kelvin-sense pcb connections between the sense resistor and the ltc2925s sensep and sensen pins are strongly recommended. the drawing in figure 22 illustrates the correct way of making connections between the ltc2925 and the sense resistor. pcb layout should be balanced and symmetrical to minimize wiring errors. in addition, the pcb layout for the sense resistor should include good thermal management techniques for optimal sense resistor power dissipation. the power rating of the sense resistor should accommodate steady-state fault current levels so that the component is not damaged before the circuit breaker trips. r fa r fb r series minimize trace length v cc ltc2925 2925 f21 fb1 gnd 0.1f dc/dc fb out irc-tt sense resistor lr251201r010f or equivalent 0.01, 1%, 1w current flow to load to sensep to sensen current flow to load track width w: 0.03" per amp on 1 oz copper 2925 f22 w figure 21. layout considerations figure 22. making pcb connections to the sense resistor
ltc2925 21 2925fc typical application external fet controls 1v supply 0.015 q1 si4412ady 0.1f c pgtmr 0.82f 10k v cc sensep sensen 3.3v v in 3.3v r onb 138k 3.3v 1v r tb1 8.66k r tb2 32.4k r fa2 41.2k 2.5v slave2 master r fb2 88.7k r ta2 215k r tb3 53.6k r ta3 348k r ta1 48.7k r ona 100k rampbuf track1 track2 track3 fb2 gate ltc2925 pgtmr c sdtmr 0.082f sdtmr c sctmr 0.41f sctmr gnd 2925 ta03a ramp r fa3 100k 1.5v slave3 r fb3 86.6k dc/dc in fb = 0.8v out dc/dc in fb = 0.8v run/ss run/ss out fb3 3.3v pgi r fa1 35.7k 1.8v slave1 r fb1 16.5k supply monitor dc/dc in fb = 1.235v run/ss out fb1 fault on 10k v in status remote rst sd3 sd2 sd1 c gate 0.1f 10
ltc2925 22 2925fc package description gn package 24-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641) .337 ? .344* (8.560 ? 8.738) gn24 (ssop) 0204 12 3 4 5 6 7 8 9 10 11 12 .229 ? .244 (5.817 ? 6.198) .150 ? .157** (3.810 ? 3.988) 16 17 18 19 20 21 22 23 24 15 14 13 .016 ? .050 (0.406 ? 1.270) .015 .004 (0.38 0.10) 45 0 ? 8 typ .0075 ? .0098 (0.19 ? 0.25) .0532 ? .0688 (1.35 ? 1.75) .008 ? .012 (0.203 ? 0.305) typ .004 ? .0098 (0.102 ? 0.249) .0250 (0.635) bsc .033 (0.838) ref .254 min recommended solder pad layout .150 ? .165 .0250 bsc .0165 .0015 .045 .005 *dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side **dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale
ltc2925 23 2925fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. package description uf package 24-lead plastic qfn (4mm 4mm) (reference ltc dwg # 05-08-1697) 4.00 0.10 (4 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wggd-x)?to be approved 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 24 23 1 2 bottom view?exposed pad 2.45 0.10 (4-sides) 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uf24) qfn 0105 recommended solder pad pitch and dimensions 0.70 0.05 0.25 0.05 0.50 bsc 2.45 0.05 (4 sides) 3.10 0.05 4.50 0.05 package outline pin 1 notch r = 0.20 typ or 0.35 45 chamfer
ltc2925 24 2925fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com linear technology corporation 2004 lt 1207 rev c ? printed in usa related parts typical application electronic circuit breaker monitors slave output q1 si4412ady 0.1f c pgtmr 0.82f 10k v cc sensep sensen 3.3v v in 3.3v r onb 138k v in r tb1 16.5k r tb2 88.7k r fa2 41.2k 2.5v slave2 master r fb2 88.7k r ta2 41.2k r tb3 86.6k r ta3 100k r ta1 13k r ona 100k rampbuf track1 track2 track3 fb2 gate ltc2925 pgtmr c sdtmr 0.082f sdtmr c sctmr 0.41f sctmr gnd 2925 ta03b ramp r fa3 100k 1.5v slave3 r fb3 86.6k dc/dc in fb = 0.8v out dc/dc in fb = 0.8v run/ss run/ss out fb3 3.3v pgi r fa1 35.7k 1.8v slave1 r fb1 16.5k supply monitor dc/dc in fb = 1.235v run/ss out fb1 fault on 10k v in status remote rst 0.015w sd3 sd2 sd1 c gate 0.1f 10 part number description comments ltc2900 quad voltage monitor in msop and dfn 16 user selectable combinations, 1.5% threshold accuracy ltc2901 quad voltage monitor with watchdog 16 user selectable combinations, adjustable timers ltc2902 quad voltage monitor with adjustable reset 5%, 2.5%, 10% and 12.5% selectable supply tolerances ltc2920 power supply margining controller single or dual, symmetric/asymmetric high and low margining ltc2921/ltc2922 power supply tracker with input monitors includes three (ltc2921) or five (ltc2922) remote sense switches ltc2923 power supply sequencing/tracking controller controls two supplies without fets, msop-10 and dfn-12 packages

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